(here at Medium-Size-Fabless-Semi-Inc, I'm in the middle of revving a bunch of parts that are about 10 years old, not because we want to add new features to them but because the process node is so obsolete it's becoming difficult to fab. Yes, they're getting new features, but that's not the primary driver of business)
On the other hand, because parts are physical objects, you can charge money for them. Piracy is .. not nonexistant (ask FTDI) but not a major concern.
There are some interesting corners for rapid-rev electronics, but there's a decision tree:
- can I do this with a microcontroller?
- if not, how about an FPGA?
- ok, there really is no alternative to ASIC, is the market size enough to support that?There is definitely a huge gap, where hardware people spend a great deal of time creating and testing things, that they then want to manufacture for long enough to pay it back. It seems like on the (web) software side, people want to try something out (maybe over a weekend), launch it quickly, then shut it down when they figure out it's not going anywhere (the Google approach).
Everyone hates change, when the fallout of the outcome of the change is on THEM specifically and impacts their career. That's why SW people keep picking Oracle, Microsoft, Google, etc
With an appropriate debug core in the same wafer, designers who'd completed a tape-out could connect to their chip well enough to repeat their design-verification tests on this real hardware, remotely even (no need to physically handle the device 'til you're certain it's working.) Once satisfied, customers could promote their design to be bonded out for installation into their PCB.
"Sure thing boss, we'll add an extra USART core to this afternoon's tape out."
You can do that, but it’s going to turn out poorly.
Plus, the only way fab costs become achievable are MPW runs which don't have adequate demand for multiple daily runs. The ones I've used run a few processes each month, rotating between most of them on a bimonthly to quarterly basis. They just don't fill up fast enough. But I'm small time fabless so maybe I'm missing something.
Part of the delay is really just commercial. Fabs are optimized for utilization - throughput, not latency. A fab operator will prefer to queue up a load of work with as few gaps as possible, and your shuttle service run has to fit in one of the gaps. If you're NVIDIA and you've already booked the fab, there might not be so much delay. But not zero.
Nice little backgrounder: https://siliconmasters.co/blogs/our-blog/how-photomasks-for-...
If there was a realistic way even to go from bare wafers to non-trivial custom chips in a small-batch fashion, you can bet there would be a cottage industry around it. I would love to live in a world where I could manufacture custom silicon as easily as I can manufacture a custom PCB or custom mechanical part.
But as it stands, quick-turn, rapid-proto "micro" fabs are obscenely expensive, to the extent that if you aren't absolutely certain you need the performance gains from custom silicon, justified by years of R&D that confirms the inadequacy of a multi-chip solution, then the idea is killed before any layout engineer is contacted.
Microfabs are either operated by research institutes, or they're booked solid for years, and basically printing money.
They may have lasers, electron microscopes, probes, etc on-site for testing what Intel or TSMC ship them and verify research results, but that's pretty far away from a "cottage industry".
Intel and Samsung are the true "cottage industries" as they do full vertical integration of IP, R&D and manufacturing under the same roof.
IMEC is more like the UN of semi companies, a place for them to come together, talk, share knowledge and results and decide industry standardisation based on that.
An SBIR is just a cost effective way for the government to put a number of PhDs/engineers to work on a problem.
Shorter for a metal only change.
I remember hearing some company trying for the speed
The fact of the matter is that we're dealing with physical and chemical processes. It simply takes time for atoms to move across space. In many steps of the semiconductor fab process we are literally building up the chip by single-atom thick layers.
There's very finite limits to how fast you can throw atoms at a substrate. There are finite limits to how much time a photoresist must be exposed. There are finite limits to how fast chemicals can etch the surface. You can only saw a wafer so fast, you can only physically transport dice through space so fast.
These are problems that the entire industry wants to solve. These are problems at the bleeding edge of physics. This is not something a startup is going to solve, purely because you need to already have an entire semiconductor fab to iterate in.
They do this, it's called a multi-project wafer (it's on Wikipedia). It doesn't help with lead time of course. As far as I know tape-out cost is a lot cheaper (if your design is microcontroller-scale) but still in the $100k+ region.
One place I worked at did fast iteration by pushing as much of the risk as they could off the silicon and by using several distinct ASICs instead of a single monolithic one which would have had better performance on its own. Gave them the ability to rev the different parts at the rate they needed it at a cost to software complexity and hardware compatibility and cost.
On the other hand, having it public makes exploits more likely since everyone can take a look.
For software this is beneficial, any fixed bug or exploit is then available to everyone and can be easily deployed.
I'm not very familiar with hardware but it seems like it would require new chips to be manufacturered to really fix any issues.
Everyone can take a look, but not everyone will spend money to produce their own. So this will improve security, not reduce it.